EDN

Startup embeds RTL Verilog in C++ class library

Santa Cruz, Calif. – Promising a low-cost approach to chip design, startup Tenko Technologies Inc. (San Jose, Calif.) is going into beta test with CvSDL, a C++ class library for design and ...
Design-Reuse

Bluespec Updates ESL Synthesis Toolset; Offers Improved Verilog RTL Output for Practical IP Delivery Vehicle

WALTHAM, Mass.--May 11, 2006--Bluespec Inc. today released the latest version of its electronic system level (ESL) Synthesis software, offering a practical delivery vehicle for intellectual property ...
Design-Reuse

Concept Engineering Introduces RTLvision PRO to Help Designers of IP-based System-on-Chip Reach Faster RTL Code Closure

FREIBURG, Germany - July 6, 2006 - Concept Engineering today announced the release of RTLvision¢â PRO, a customizable tool to help designers of intellectual property (IP)-based system-on-chip reduce ...
Electronic Design

Reduce Power in Chip Designs with Sequential Clock Gating

Clock gating is one of the most frequently used techniques in RTL to reduce dynamic power consumption without affecting the functionality of the design. One method involves inserting gating conditions ...
Semiconductor Engineering

Top Five Trends In RTL Signoff

The “shift left” of the development cycle is critical for the huge, complex chips used in such applications as AI and high-performance computing (HPC). Identifying design issues at the netlist stage ...